1. Field of the Invention
This invention relates to solid state imagers and in particular to the readout of image information from charge transfer device arrays.
2. Description of the Prior Art
One of the most useful solid state image sensors is the CID (charge injection device) array. Such an array comprises a matrix of CID storage sites in which signal charges are collected in proportion to the intensity of incident radiation forming an image focused onto the array. The CID array has good antiblooming capabilities, is immune from image burn and has a higher modulation transfer function than other charge transfer devices such as CCDs. Despite these advantages, however, difficulties have been experienced in accurately reading the magnitudes of the charges collected at the discrete sites.
These difficulties can be best understood by referring to FIG. 1 which illustrates a conventional CID array and readout circuitry typically used for sensing the charges collected. The array 1 comprises a substrate of semiconductor material of one conductivity type supporting a layer of insulator material on which are formed a multiplicity of conductive pads. The array is geometrically divided into a plurality of charge storage sites, such as that indicated at 2, for collection of radiation-generated minority carriers. Each of the sites includes a pair of the pads, designated a row pad 3 and a column pad 4, and each pad defines a CIS (conductor, insulator, semiconductor) capacitive cell comprising the pad itself and the underlying portions of the insulator and semiconductor layers.
The two pads at each site are closely coupled, as is known in the art, to enable charge to be transferred between the capacitive cells in the site. The row pads in each row are electrically connected to a respective row line 5. Similarly, the column pads in each column are electrically connected to a respective column line 6. The row and column lines are each connected to a respective field effect transistor (FET) switch to enable individual accessing of the sites at selected row/column coordinates. The row lines are connected to row select switches S.sub.Vm, where m designates the row number and the column lines are connected to column select switches S.sub.Hn, where n designates the column number. FET switches S.sub.Rm, connecting respective row lines to a terminal 13 when they are turned on, are provided to enable the simultaneous application of any desired reference potential to all row lines. These switches are turned on by applying a gate signal to their gates through a terminal 14.
Readout of image intensity information from the array is accomplished by applying vertical select pulses to the gates of the FETs connected to the row lines 5, and horizontal select pulses to the gates of the FETs connected to the column lines 6. The vertical and horizontal select pulses are applied in a predetermined sequence to effect sensing of the charges stored at all of the sites. The vertical select pulses are produced by a vertical shift register 7. These pulses sequentially select pairs of rows by turning on pairs of the FETs connected to the row lines, each pair including a FET connected to an odd-numbered row line and one connected to an even-numbered row line. Vertical enable signals VEO and VEE are applied during each vertical select pulse to two row terminals 9 and 10, respectively, and through the FETS connected to the selected pair of rows. The voltage levels of these signals are first established at magnitudes which effect distribution of the charges at the sites in the selected pair of rows such that one of the rows is enabled to be read and then established at magnitudes which effect redistribution of the charges such that the other selected row is enabled to be read.
While each row is thus enabled, the horizontal select pulses are produced by a horizontal shift register 8. These pulses successively select pairs of columns by turning on pairs of the FETs connected to the column lines, each pair including a FET connected to an odd-numbered column line and one connected to an even-numbered column line. During each horizontal select pulse, horizontal enable signals HEO and HEE are twice applied to two column terminals 11 and 12, respectively, and through the FETs connected to the selected pair of columns to effect sequential reading of the signal charges in the two sites located at the intersections of the selected columns and the enabled row. During the first application of the signals their magnitudes are established at a first set of voltage levels which effect injection into the substrate of the signal charge in the odd-column site. This injection causes production on one of the pads of the odd-column site of a signal representative of the magnitude of the signal charge injected at the site. During the second application of the horizontal enable pulses their magnitudes are established at a second set of voltage levels which effect injection into the substrate of the signal charge in the even-column site. This injection causes production on one of the pads of the even-column site of a signal representative of the magnitude of the signal charge injected at the site.
As the horizontal shift register sequentially selects pairs of columns and horizontal enable signals are applied, as described above, a signal representative of the signal charge injected at each site is successively produced on either the row or the column pad at each site in the row enabled to be read. The particular magnitudes chosen for the vertical and horizontal enable pulses determine the specific manner in which charge is distributed and redistributed at the site and consequently determine whether the changes in charge are produced on the row or the column pads. These changes in charge will be sensed at the row terminal connected to the enabled row in the former case and at the two column terminals in the latter case.
Techniques have been developed both for sensing the signals representing the injected charge at the column terminals (column read techniques) and for sensing such signals at the row terminals (row read techniques). Output signals produced by these techniques, however, contain noise components which it is desirable to eliminate. In the case of the column read techniques parasitic capacitance in the transistor switches used to connect the column pads to the column terminals couple switching transient signals from the horizontal shift register to the column terminals, and these transient signals appear in the output signal as a noise component commonly known as pattern noise.
It has been recognized that the pattern noise is duplicated each time the column switches are turned on to read a particular column. This duplication has been utilized in prior art attempts to eliminate pattern noise by reading each row twice. The first time a given row is read the output signal produced includes both signal voltages representing the magnitudes of signal charges injected at the individual sites and the pattern noise. The second time the row is read the output signal produced ideally includes only the pattern noise, because the charge collected at each site in the row in the short interval between the successive readings is normally too significant to effect production of any appreciable signal voltages during injection thereof. The pattern noise is eliminated by delaying the output signal produced during the first reading of a row, to cause time alignment with the output signal produced during the second reading, and by taking the difference between the magnitudes of the two signals.
The above-described delaying technique works well if the signal charge collected between successive readings is indeed insignificant, but this assumption is not valid for images with certain characteristics. For example, images including fast-moving light sources or light sources of rapidly changing intensity will cause the sudden collection of substantial signals charge in the affected sites in the row between successive readings. In this situation, the pattern noise will be eliminated, but spurious noise caused by these sudden collections of signal charge appears in the output signal.
In the case of the row read techniques the pattern noise must also be eliminated because it is coupled from the column lines to the row lines by the closely coupled row and column pads and by capacitance at crossover points of the row and column lines. Such elimination can be effectively accomplished by use of this technique, however, because information can be simultaneously read from two selected rows at the row terminals. By appropriately manipulating the voltage levels of the vertical and horizontal enable signals the charges in each site of the two selected rows can be continually redistributed such that the signals representing the injected charges and the pattern noises are sensed at one row terminal during reading of the row connected thereto while the pattern noise only is sensed at the other row terminal. The pattern noise is eliminated by producing an output signal representative of the real time difference between the magnitudes of the signals sensed at the two terminals.
Despite the success with which pattern noise can be eliminated by use of row read techniques, prior art adaptations thereof utilize sequences of enable signal voltage manipulations which introduce additional problems. For example, some row read techniques manipulate the voltage levels of the horizontal enable signals such that the voltages on the column lines are successively changed from a low-level charge collection potential to a higher-level charge redistribution potential, and the higher-level potential is maintained until the last column is read. After a substantial number of the column pads in the array have been raised to this potential, the potential of the unselected row pads tends to increase to a potential sufficient to cause premature injection of signal charges contained thereunder. To avoid such loss of signal charge it has been found necessary to add additional circuitry to the already complex CID array to clamp the unselected rows to a potential below that at which injection occurs. Because of this requirement for additional circuitry, this row read technique is not useable with conventional arrays such as that depicted in FIG. 1.
In other adaptations of the row read technique the voltage levels of the enable signals are manipulated such that the signal charges from all sites in the row being read are simultaneously injected into the semiconductor substrate. Changes in the row pad voltages representative of the signal charges injected at the respective sites are then sensed. Because of the substantial influx of charge into the semiconductor material a significant increase in voltage in experienced on all pads of the array. This voltage causes a temporary offset in the voltage levels on the row and column lines and causes an error in all output signals produced before the injected charge is dissipated in the substrate.